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| CY62157E MoBL(R) 8-Mbit (512K x 16) Static RAM Features * Very high speed: 45 ns -- Industrial: -40C to +85C -- Automotive-E: -40C to +125C * Wide voltage range: 4.5V-5.5V * Ultra low standby power -- Typical Standby current: 2 A -- Maximum Standby current: 8 A (Industrial) * Ultra low active power * * * * * -- Typical active current: 1.8 mA @ f = 1 MHz Ultra low standby power Easy memory expansion with CE1, CE2 and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb-free 44-pin TSOP II and 48-ball VFBGA package also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input or output pins (IO0 through IO15) are placed in a high impedance state when: * Deselected (CE1HIGH or CE2 LOW) * Outputs are disabled (OE HIGH) * Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) * Write operation is active (CE1 LOW, CE2 HIGH and WE LOW) To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the "Truth Table" on page 9 for a complete description of read and write modes. Functional Description[1] The CY62157E is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 512K x 16 RAM Array SENSE AMPS IO0-IO7 IO8-IO15 CE2 Power Down Circuit CE1 COLUMN DECODER BHE WE A11 A12 A13 A15 A14 A17 A18 A16 BHE BLE CE2 CE1 OE BLE Notes 1. For best practice recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines. Cypress Semiconductor Corporation Document #: 38-05695 Rev. *E * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised April 27, 2007 CY62157E MoBL(R) Product Portfolio Power Dissipation Product Range Min CY62157ELL CY62157ELL Industrial Automotive 4.5 4.5 VCC Range (V) Typ[2] 5.0 5.0 Max 5.5 5.5 45 55 Speed (ns) Typ[2] 1.8 1.8 Operating ICC, (mA) f = 1 MHz Max 3 4 f = fmax Typ[2] 18 18 Max 25 35 Standby, ISB2 (A) Typ[2] 2 2 Max 8 30 Pin Configuration The following pictures show the TSOP II and VFBGA pinouts.[3, 4] TSOP II Top View A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 A8 A9 A10 A11 A12 A13 1 BLE IO 8 IO 9 VSS VCC IO 14 IO 15 A18 2 OE BHE IO 10 IO11 IO 12 IO 13 NC A8 VFBGA Top View 4 3 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 IO 1 IO3 IO 4 IO 5 WE A11 6 CE2 IO 0 IO 2 Vcc Vss IO 6 IO 7 NC A B C D E F G H Notes 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 3. NC pins are not connected on the die. 4. The 44-pin TSOP II package has only one chip enable (CE) pin. Document #: 38-05695 Rev. *E Page 2 of 12 CY62157E MoBL(R) Maximum Ratings Exceeding maximum ratings may shorten the battery life of the device. User guidelines are not tested. Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied ........................................... -55C to + 125C Supply Voltage to Ground Potential .......................................................... -0.5V to 6.0V DC Voltage Applied to Outputs in High-Z State[5, 6] ........................................... -0.5V to 6.0V DC Input Voltage[5, 6] ........................................-0.5V to 6.0V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage .......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current .................................................... > 200 mA Operating Range Device CY62157ELL Range Industrial Ambient Temperature -40C to +85C VCC[7] 4.5V to 5.5V Automotive -40C to +125C Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Test Conditions IOH = -1 mA IOL = 2.1 mA VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V GND < VI < VCC 2.2 -0.5 -1 -1 18 1.8 2 45 ns (Industrial) Min 2.4 0.4 VCC + 0.5 0.8 +1 +1 25 3 8 2.2 -0.5 -4 -4 18 1.8 2 Typ[2] Max 55 ns (Automotive) Min 2.4 0.4 VCC + 0.5 0.8 +4 +4 35 4 30 A Typ[2] Max Unit V V V V A A mA Output Leakage GND < VO < VCC, Output Disabled Current VCC Operating Supply Current Automatic CE Power Down Current -- CMOS Inputs Automatic CE Power Down Current -- CMOS Inputs f = fmax = 1/tRC VCC = VCC(max) IOUT = 0 mA f = 1 MHz CMOS levels CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V, VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE, BHE, BLE and WE), VCC = VCC(max) CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = VCC(max) ISB1 ISB2 [8] 2 8 2 30 A Capacitance[9] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Notes 5. VIL(min) = -2.0V for pulse durations less than 20 ns for I < 30 mA. 6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 7. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Only chip enables (CE1 and CE2) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 9. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05695 Rev. *E Page 3 of 12 CY62157E MoBL(R) Thermal Resistance [9] Parameter JA JC Description Test Conditions TSOP II 77 13 VFBGA 72 8.86 Unit C/W C/W Thermal Resistance Still Air, soldered on a 3 x 4.5 inch, (Junction to Ambient) two-layer printed circuit board Thermal Resistance (Junction to Case) AC Test Loads and Waveforms Figure 1. AC Test Loads and Waveforms VCC OUTPUT R1 3V 30 pF INCLUDING JIG AND SCOPE R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Values 1800 990 639 1.77 Unit V Parameters R1 R2 RTH VTH Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR [8] tCDR [9] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC=2V, CE1> VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Industrial Automotive Min 2 Typ [2] Max 8 30 Unit V A ns ns 0 tRC tR [10] Data Retention Waveform[11] Figure 2. Data Retention Waveform DATA RETENTION MODE VCC CE1 or BHE.BLE or CE2 Notes 10. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 11. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. VCC(min) tCDR VDR > 2V VCC(min) tR Document #: 38-05695 Rev. *E Page 4 of 12 CY62157E MoBL(R) Switching Characteristics Over the Operating Range[12, 13] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[16] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z[14, 15] 10 WE HIGH to Low-Z[14] 45 35 35 0 0 35 35 25 0 18 10 55 40 40 0 0 40 40 25 0 20 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW-Z[14] OE HIGH to High-Z[14, 15] CE1 LOW and CE2 HIGH to CE1 HIGH and CE2 LOW to Low-Z[14] High-Z[14, 15] 0 45 45 10 18 10 20 10 18 0 55 55 5 18 10 20 10 45 22 5 20 45 45 10 55 25 55 55 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description 45 ns (Industrial) Min Max 55 ns (Automotive) Min Max Unit CE1 LOW and CE2 HIGH to Power Up CE1 HIGH and CE2 LOW to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low-Z[14] BLE/BHE HIGH to HIGH-Z[14, 15] Notes 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 4. 13. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 38-05695 Rev. *E Page 5 of 12 CY62157E MoBL(R) Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[17, 18] Figure 3. Read Cycle No. 1 tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled)[18, 19] Figure 4. Read Cycle No. 2 ADDRESS tRC CE1 CE2 tACE BHE/BLE tDBE tLZBE OE tDOE DATA VALID tHZOE HIGH IMPEDANCE tHZBE tPD tHZCE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 17. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 18. WE is HIGH for read cycle. 19. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05695 Rev. *E Page 6 of 12 CY62157E MoBL(R) Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[16, 20, 21] Figure 5. Write Cycle No. 1 tWC ADDRESS tSCE CE1 CE2 tAW WE tSA tPWE tHA BHE/BLE tBW OE DATA IO NOTE 22 tHZOE tHD tSD VALID DATA Write Cycle No. 2 (CE1 or CE2 Controlled)[16, 20, 21] Figure 6. Write Cycle No. 2 tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA WE BHE/BLE tBW OE DATA IO NOTE 22 tHZOE tSD VALID DATA tHD Notes 20. Data IO is high impedance if OE = VIH. 21. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 22. During this period, the IOs are in output state. Do not apply input signals. Document #: 38-05695 Rev. *E Page 7 of 12 CY62157E MoBL(R) Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[21] Figure 7. Write Cycle No. 3 tWC ADDRESS tSCE CE1 CE2 BHE/BLE tAW tSA WE tBW tHA tPWE tSD DATA IO NOTE 22 VALID DATA tHD tHZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[21] Figure 8. Write Cycle No. 4 tWC ADDRESS tLZWE CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA IO NOTE 22 VALID DATA tHD tBW tHA Document #: 38-05695 Rev. *E Page 8 of 12 CY62157E MoBL(R) Truth Table CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High-Z High-Z High-Z Data Out (IO0-IO15) Data Out (IO0-IO7); High-Z (IO8-IO15) High-Z (IO0-IO7); Data Out (IO8-IO15) High-Z High-Z High-Z Data In (IO0-IO15) Data In (IO0-IO7); High-Z (IO8-IO15) High-Z (IO0-IO7); Data In (IO8-IO15) Mode Deselect/Power Down Deselect/Power Down Deselect/Power Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 45 55 Ordering Code CY62157ELL-45ZSXI CY62157ELL-55ZSXE CY62157ELL-55BVXE Package Diagram 51-85087 51-85087 51-85150 Package Type 44-pin Thin Small Outline Package Type II (Pb-free) 44-pin Thin Small Outline Package Type II (Pb-free) 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Operating Range Industrial Automotive Contact your local Cypress sales representative for availability of these parts. Document #: 38-05695 Rev. *E Page 9 of 12 CY62157E MoBL(R) Package Diagrams Figure 9. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 8.000.10 8.000.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 6.000.10 A 1.875 0.75 3.75 B 6.000.10 0.55 MAX. 0.25 C 0.15(4X) 0.210.05 0.10 C 1.00 MAX SEATING PLANE 0.26 MAX. C 51-85150-*D Document #: 38-05695 Rev. *E Page 10 of 12 CY62157E MoBL(R) Package Diagrams (continued) Figure 10. 44-Pin TSOP II, 51-85087 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05695 Rev. *E Page 11 of 12 (c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62157E MoBL(R) Document History Page Document Title: CY62157E MoBL(R), 8-Mbit (512K x 16) Static RAM Document Number: 38-05695 REV. ** *A ECN NO. Issue Date 291273 457689 See ECN See ECN Orig. of Change PCI NXR Description of Change New data sheet Added Automotive Product Removed Industrial Product Removed 35 ns and 45 ns speed bins Removed "L" bin Updated AC Test Loads table Corrected tR in Data Retention Characteristics from 100 s to tRC ns Updated the Ordering Information and replaced the Package Name column with Package Diagram Added Industrial Product (Final Information) Removed 48 ball VFBGA package and its relevant information Changed the ICC(typ) value of Automotive from 2 mA to 1.8 mA for f = 1MHz Changed the ISB2(typ) value of Automotive from 5 A to 1.8 A Modified footnote #4 to include current limit Updated the Ordering Information table Added 48 ball VFBGA package Updated Logic Block Diagram Added footnote #3 Updated the Ordering Information table Added footnote #9 related to ISB2 and ICCDR Added footnote #14 related AC timing parameters Converted Automotive specs from preliminary to final *B 467033 See ECN NXR *C 569114 See ECN VKN *D *E 925501 1045801 See ECN See ECN VKN VKN Document #: 38-05695 Rev. *E Page 12 of 12 |
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